Anti-parallel SBD: Oversizing It Actually Wastes Power
—Why the freewheeling diode next to a SiC MOSFET may have lower losses with a smaller rating than with a larger one
The default instinct for anti-parallel SBD selection is "leave a bigger margin." But SBD junction capacitance grows with rated current, and that capacitance is charged and discharged on every switching event. The loss saved by eliminating reverse recovery can be given back through the extra junction capacitance. An IEEE study quantified this: in SiC motor-drive inverters, smaller-rated SBDs deliver better overall performance across a wide operating range.
1. The Anti-Parallel SBD Contradiction: Reverse Recovery Saved, Junction Capacitance Added
The body diode of a SiC MOSFET carries freewheeling current during dead time, but its reverse recovery and bipolar degradation risk push engineers toward an anti-parallel SiC SBD. An SBD is a unipolar device with no minority-carrier storage, so reverse recovery essentially disappears and dead-time loss drops.
But the SBD is not "free." Its junction capacitance adds to the MOSFET's output capacitance, and this extra charge must be charged and discharged by the gate driver on every turn-on and turn-off. The larger the rated current, the larger the die area, and the larger the junction capacitance. Choosing a bigger device with "ample current margin and lower VF" can mean the loss saved from reverse recovery is offset—or even reversed—by the added junction capacitance.
A 2023 IEEE study broke this contradiction down: in SiC motor-drive voltage-source inverters, the SBD eliminates reverse recovery and reduces dead-time loss, but the "additional capacitance brought by SBD" increases switching loss. The study compared four SBDs with different ratings and concluded that inverters using smaller-rated SBDs delivered better overall performance across a wide operating range, with optimized selection improving efficiency by up to 1 percentage point versus conventional strategies.
2. Why Motor Drives Are Especially Sensitive to This Contradiction
Industrial servo and motor drives typically switch at 10–20kHz, which does not look high, but the inverter's switching events accumulate continuously. On every switching event, the SBD junction capacitance participates in a charge transfer, and this loss is proportional to switching frequency and to the SBD capacitance. In continuously running servos or variable-frequency drives, the total is not negligible.
More importantly, a large share of motor-drive operation falls in the light- and medium-load range. Under these conditions, SBD conduction loss is not dominant, and the weight of switching loss and dead-time-related loss rises. The VF advantage of a large-rated SBD at full load is diluted by its larger junction capacitance at light load. A smaller-rated SBD has a lower capacitance penalty at light and medium load, making it easier for the overall loss curve to land at a better point.
This also explains why the silicon IGBT-era instinct of "leave twice the margin on maximum current" needs to be re-examined for SiC anti-parallel SBD selection.
3. Hypersemi's Entry: 650V Tier, Two Package Paths—PDFN8×8 and TO-220AC
Motor-drive DC buses are typically at the 400V level, and 650V provides sufficient margin. Two Hypersemi SiC SBDs in this tier map directly to the anti-parallel selection principle of "do not over-size the rating."
CR1565PEX100, 650V / 15A / VF 1.5V / PDFN8×8, controls die area and junction capacitance at the 15A rating in a PDFN8×8 package; the surface-mount form matches the PCB-based trend in compact servo-drive power stages. For inverters targeting small-to-medium servo or variable-frequency applications, the 15A tier covers freewheeling needs in single-phase or small three-phase topologies without paying a capacitance penalty for unused current margin. CR1065TCX100, 650V / 10A / VF 1.39V / TO-220AC, narrows the rating further; VF 1.39V provides competitive conduction-loss performance in the 650V tier, and the TO-220AC through-hole package suits designs with an existing thermal path.
Model | VRRM / IF / VF | Package | Positioning in Anti-Parallel SBD Selection |
|---|---|---|---|
CR1565PEX100 | 650V / 15A / 1.5V | PDFN8×8 | Small-to-medium servo/VFD, compact surface-mount power stage, compromise between junction capacitance and freewheeling capability |
CR1065TCX100 | 650V / 10A / 1.39V | TO-220AC | Through-hole layout or lower-VF requirement, 10A tier controls junction-capacitance penalty |
Both models can be filtered by VRRM, IF, VF, and package on the Hypersemi SiC diode product page (https://www.hypersemi.com.cn/products/sic-diodes).
4. How to Verify Whether "Smaller" Is Really Better
Anti-parallel SBD selection cannot be settled by simply "going one size down." The correct verification sequence is: first determine the actual freewheeling current and dead time the SBD sees in the target inverter topology, then run double-pulse comparisons across candidate ratings and observe the loss difference caused by junction-capacitance charge/discharge in the turn-on and turn-off waveforms. The IEEE study used a four-rating comparison with loss calculation; in engineering practice, at minimum, converge between two adjacent current tiers rather than jumping straight to the largest margin.
If double-pulse results show that the smaller-rated tier already matches or beats the larger one in overall loss, there is no reason to keep paying the junction-capacitance penalty for current margin you will never use.
Device parameters in this article are subject to Hypersemi official datasheets. Anti-parallel SBD selection must be verified on a double-pulse platform in conjunction with the specific inverter topology, dead-time strategy, and switching frequency.