Paralleling IGBTs in High-Power Converters: Why Two Modules That Both Meet Specs Can Still Share Current Poorly
——Why parallel consistency matters more than a single module looking good: two Hypersemi 200A modules in the same package and at the same current show different loss distributions
When expanding current by paralleling, engineers often check each module individually to confirm that its VCE(sat) and Eon/Eoff fall “within specification.” But current sharing in a parallel system depends on the parameter distribution spread between paired modules, not on the typical value of a single unit. Small differences in static VCE(sat) cause steady-state current offset, while differences in dynamic Eon/Eoff create more significant current imbalance during switching transients, ultimatel
1. The Hidden Cost of Paralleling: Single-Unit “Compliance” Masks System-Level Current Imbalance
Power levels in high-power converters and UPS systems continue to rise. When a single module’s current is insufficient, paralleling is the most direct way to expand current. In a parallel system, however, inconsistent static and dynamic parameters force the effective output current to be derated, reducing reliability and increasing cost. A commonly cited quantitative relationship is that when two chips are paralleled, the maximum allowable current per chip may drop to about 80% of the single-device rating; the more devices in parallel, the more significant the derating.
The problem is that this derating is not visible in a single module’s datasheet. Checking VCE(sat) “within range” and Eon/Eoff “not exceeding the maximum” easily leads to the conclusion that “each unit meets specification, so paralleling is fine.” But “each unit meets specification” and “the pair is consistent” are two different propositions. Differences in static VCE(sat) directly determine which device carries more current in steady state; differences in dynamic Eon/Eoff redistribute the current burden during every switching transient and gradually accumulate into junction-temperature dispersion over thermal cycling.
2. Two Modules in the Same Class, with Loss Distributions Moving in Opposite Directions
In Hypersemi’s 1200 V / 200 A half-bridge portfolio, HGF200MP120X100 (EconoDUAL3) and HGF200MA120X100 (34 mm) are a useful comparison for understanding parallel consistency. Their voltage, current, and topology are identical, but their loss characteristics show directional differences.
The typical VCE(sat) of HGF200MP120X100 is 1.85 V at 25°C and approximately 2.2 V at 150°C; its Eon/Eoff under datasheet test conditions show a relatively pronounced turn-off loss characteristic. The typical VCE(sat) of HGF200MA120X100 is 2.2 V at 25°C and approximately 2.5 V at 150°C; its Eon/Eoff at 150°C are 37 mJ and 15.2 mJ respectively, with turn-on loss significantly higher than turn-off loss. Its overall loss distribution forms a clear contrast with the MP model.
The VCE(sat) values of the two modules differ by about 0.35 V at room temperature. At 200 A, this means a noticeable offset in static conduction voltage drop. If they are treated as “interchangeable 200 A class” devices and paralleled directly, steady-state current will naturally concentrate in the device with lower VCE(sat). The dynamic side diverges even more sharply: the MP model has a higher share of turn-off loss, while the MA model has a higher share of turn-on loss. During switching transients, their current waveforms deviate from the equal-sharing line in different ways on the turn-on and turn-off edges.
This does not mean either module is “non-compliant”—both are reasonable designs for their intended operating conditions. The MP model targets UPS and motor drives; the MA model targets UPS, high-power converters, and high-frequency power supplies. Each has been loss-optimized for specific scenarios. The issue is precisely that when two modules optimized for different operating conditions are placed into the same parallel array, “each meets specification” does not automatically become “the pair is consistent.”
3. What to Check in Parallel Selection: Distribution Width, Not Typical Values
In parallel design, the more meaningful check is the difference in VCE(sat) and Eon/Eoff between paired modules, not whether each unit’s typical value looks good. On the static side, the VCE(sat) pairing difference should be as small as possible to suppress steady-state current offset; on the dynamic side, Eon/Eoff pairing consistency directly determines current distribution and junction-temperature dispersion during switching transients. HGF200MP120X100 and HGF200MA120X100 should not be placed into the same parallel group simply because both are “200 A”; instead, pairing feasibility should be re-evaluated according to the loss weighting under actual operating conditions, or batches with loss characteristics in the same direction should be selected for pairing.
For higher-power parallel arrays, HGF450HF170X100 (1700 V / 450 A half-bridge) provides a reference in which consistency requirements are further tightened: as per-module current capability and the number of parallel devices increase, the influence of pairing parameter distribution width on the system derating factor is amplified. The more devices in parallel, the deeper the derating, and the more the general advice to “use the same batch and add current-sharing resistors” becomes insufficient to replace checking at the parameter-distribution level.
The design goal of parallel current expansion is not to make each module look good individually, but to make paired modules sufficiently “alike” in both static and dynamic dimensions. The VCE(sat) difference and the Eon/Eoff distribution width are the boundaries that determine whether a parallel system can output close to its rated value. Hypersemi’s 1200 V / 200 A and 1700 V / 450 A half-bridge portfolios provide complete loss parameters, allowing this pairing check to be completed at the selection stage.
Explore the full Hypersemi IGBT module series, filter by voltage, current, topology, and package, download datasheets, and put VCE(sat) and Eon/Eoff pairing differences into the parallel calculation table.
The device parameters in this article are based on the official Hypersemi datasheet. Parallel current-sharing design must take into account gate-drive symmetry, layout parasitic parameters, and the actual load profile, and pairing verification and derating calculation should be completed at the system level.