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Hardware noise issues are four words that every circuit board designer will hear. To solve the problem of hardware noise, it often takes several hours to conduct laboratory tests in order to identify the culprit. However, it is eventually found that the noise is caused by the improper layout of the switching power supply. Solving such problems may require designing a new layout, resulting in product delays and increased development costs.

This article will provide guidelines on the layout and routing of printed circuit boards (PCBS) to help designers avoid such noise problems. The layout of the switch regulator as an example adopts the dual-channel synchronous switch controller ADP1850. The first step is to determine the current path of the regulator. Then, the current path determines the position of the device in this low-noise layout and routing design.

PCB Layout and Routing Guide

The first step: Determine the current path

In the design of switching converters, the high-current path and the low-current path are very close to each other. Alternating current (AC) paths carry spikes and noise, high direct current (DC) paths generate considerable voltage drops, and low current paths are often sensitive to noise. The key to proper PCB layout and routing lies in determining the critical path, then arranging the components, and providing sufficient copper area to prevent high current from damaging low current. Poor performance is manifested by ground rebound and noise injection into the IC and the rest of the system. 

Figure 1 shows a design of a synchronous step-down regulator, which includes a switch controller and the following external power supply devices: high-end switch, low-end switch, inductor, input capacitor, output capacitor and bypass capacitor. The arrows in Figure 1 indicate the direction of the high-switching current flow. These power supply devices must be placed carefully to avoid generating poor parasitic capacitance and inductance, which could lead to excessive noise, overshoot, ringing oscillation and ground rebound.

Figure 1. Typical switching regulator (showing AC and DC current paths)

Switching current paths such as DH, DL, BST and SW should be properly arranged after leaving the controller to avoid generating excessive parasitic inductance. The high δI/δt AC switch pulse currents carried by these lines may reach more than 3 A and last for several nanoseconds. The high-current loop must be very small to minimize the output ringing oscillation as much as possible and avoid picking up additional noise.

Low-value and low-amplitude signal paths, such as compensation and feedback devices, are highly sensitive to noise. These paths should be kept far away from the key points and power supply devices to avoid injecting interference noise.

第二步：布局物理规划

PCB物理规划(floor plan)非常重要，必须使电流环路面积最小，并且合理安排电源器件，使得电流顺畅流动，避免尖角和窄小的路径。这将有助于减小寄生电容和电感，从而消除接地反弹。
 

Figure 2 shows the PCB layout of a dual-output step-down converter using the switch controller ADP1850. Please note that the layout of the power supply devices minimizes the current loop area and parasitic inductance. The dotted line represents the high-current path. Both synchronous and asynchronous controllers can use this physical planning technology. In the design of asynchronous controllers, Schottky diodes replace low-end switches.

Figure 2. PCB layout of the dual-output step-down converter using the ADP1850 controller

Step 3: Power supply devices - MOSFET and capacitors (input, bypass and output)

The current waveforms at the top and bottom power switches are a pulse with a very high δI/δt. Therefore, the paths connecting each switch should be as short as possible to minimize the noise picked up by the controller and the noise transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate these two FETs in the opposite direction SO that the switching node is on one side of this pair of FETs, and use the appropriate ceramic bypass capacitor to bypass the high-end leakage current to the low-end source. Be sure to place the bypass capacitor as close as possible to the MOSFET (see Figure 2) to minimize the inductance around the loop passing through the FET and the capacitor. 

The placement of the input bypass capacitor and the input large capacitor is crucial for controlling ground rebound. The negative terminal connection of the output filter capacitor should be as close as possible to the source of the low-end MOSFET, which helps to reduce the loop inductance that causes ground rebound. The Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors, and the recommended value range of these capacitors is from 1 μF to 22 μF. For high-current applications, an additional large-value filter capacitor should be connected in parallel, as shown in CIN in Figure 2.

Heat dissipation considerations and ground layer

Under heavy load conditions, the equivalent series resistance (ESR) of power MOSFETs, inductors and large capacitors generates a significant amount of heat. For effective heat dissipation, the example in Figure 2 places a large area of copper under these power devices. 

The heat dissipation effect of multi-layer PCBS is better than that of two-layer PCBS. To enhance heat dissipation and electrical conductivity, a 2-ounce thick copper layer should be used on the standard 1-ounce copper layer. Multiple PGND layers connected together through vias can also be helpful. Figure 3 shows that PGND layers are distributed on the top layer, the third layer and the fourth layer of a 4-layer PCB design.

Figure 3. Cross-sectional view: Connect the PGND layer to improve heat dissipation

This multi-layer formation method can isolate signals that are sensitive to noise. As shown in Figure 2, the negative terminals of the compensation device, soft-start capacitor, bias input bypass capacitor and output feedback voltage divider resistor are all connected to the AGND layer. Do not directly connect any high current or high δI/δt path to the isolated AGND layer. Youdaoplaceholder0 is a quiet stratum through which no high current flows.

  
The negative terminals of all power supply devices (such as low-end switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND layer, which carries high current.

The voltage drop within the GND layer can be quite significant, to the extent that it affects the output accuracy. Output accuracy and load regulation can be significantly improved by connecting the AGND layer to the negative terminal of the output capacitor with a wide trace (see Figure 4).

Figure 4. The connection from layer AGND to layer PGND

The AGND layer extends all the way to the output capacitor, and the AGND layer and the PGND layer are connected to the vias at the negative end of the output capacitor

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Figure 2 shows another technique for connecting the AGND and PGND layers. The AGND layer is connected to the PGND layer through a via near the negative terminal of the output large capacitor. Figure 3 shows a cross-section at a certain location on a PCB, where the AGND layer and the PGND layer are connected through a via near the negative terminal of the output large capacitor.

Current detection path

To avoid the decline in accuracy caused by interference noise, the current detection path layout of the current-mode switch regulator must be appropriate. Special attention should be paid to dual-channel applications to eliminate any crosstalk between channels.

The dual-channel step-down controller ADP1850 uses the on-resistance RDS(ON) of the low-end MOSFET as part of the control loop architecture. This architecture detects the current flowing through the low-end MOSFET between the SWx and PGNDx pins. The ground current noise in one channel may couple into adjacent channels. Therefore, it is essential to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFET to accurately detect the current. The connections to the SWx and PGNDx nodes must adopt the Kelvin detection technology, as shown in Figures 2 and 5. Note that the corresponding PGNDx trace is connected to the source of the low-end MOSFET. Do not connect the PGND layer to the PGNDx pin at will

Figure 5. Grounding technology of the two channels

In contrast, for dual-channel voltage mode controllers like ADP1829, the PGND1 and PGND2 pins are directly connected to the PGND layer through vias

Feedback and rate-limiting detection paths

The feedback (FB) and current-limiting (ILIM) pins are low-signal-level inputs, so they are sensitive to capacitive and inductive noise interference. FB and ILIM traces should be kept away from high δI/δt traces. Be careful not to let the wiring form a loop, which may lead to an increase in poor inductance. Adding a small MLCC decoupling capacitor (such as 22 pF) between the ILIM and PGND pins helps to further filter out the noise. 

Switch node

In a switching regulator circuit, the switching (SW) node is the place with the highest noise because it carries large AC and DC voltages/currents. This SW node requires a large area of copper to minimize the resistive voltage drop as much as possible. Placing the MOSFET and inductor close to each other on a copper layer can minimize the series resistance and inductance. 

Applications that are more sensitive to electromagnetic interference, switch node noise and ringing oscillation can use a small buffer. The buffer is composed of a resistor and a capacitor in series (see RSNUB and CSNUB in Figure 6), placed between the SW node and the PGND layer, which can reduce the ringing oscillation and electromagnetic interference on the SW node. Note that adding a buffer may slightly reduce the overall efficiency by 0.2% to 0.4%.

The gate drive traces (DH and DL) also need to handle high δI/δt, which often leads to ringing oscillations and overshoot. These traces should be as short as possible. It is best to wire directly and avoid using feedthrough holes. If vias must be used, two vias should be used for each trace to reduce peak current density and parasitic inductance.

  
Connecting a small resistor (approximately 2 Ω to 4 Ω) in series on the DH or DL pin can slow down the gate drive, thereby also reducing gate noise and overshoot. In addition, a resistor can also be connected between the BST and SW pins (see Figure 6). Reserving space with a 0 Ω gate resistor during the layout can enhance the flexibility for future evaluations. The increased gate resistance will prolong the rise and fall time of the gate charge, resulting in an increase in the switching power loss of the MOSFET.

Summary

Understanding the current path, its sensitivity and the appropriate placement of components is the key to eliminating the noise problem in PCB layout design. All power device evaluation boards of ADI Company adopt the above-mentioned layout and routing guidelines to achieve the best performance. The evaluation board files UG-204 and UG-205 detail the layout and wiring related to ADP1850.

  
Note that all switching power supplies have the same components and similar current path sensitivities. Therefore, the guiding principles illustrated by taking the ADP1850 for current-mode step-down regulators as an example are also applicable to the layout and wiring of voltage-mode and/or boost switch regulators.